1. Technical Field
The present disclosure relates to MOS transistors, and more specifically to air-spacer MOS transistors.
2. Discussion of the Related Art
In the forming of a MOS transistor, it is generally desired to decrease the power consumption on switching and to increase the switching speed. Such parameters especially depend on the gate-source, gate-drain, gate-source contact, and gate-drain contact capacitances.
Such stray capacitances tend to become particularly significant in the case of MOS transistors of very small size, where the gate lengths are shorter than some hundred nanometers, and especially shorter than 20 nm. Indeed, in this case, the distances between the gate, on the one hand, and the source, the drain, the source contact, and the drain contact, on the other hand, become extremely small. A solution to decrease such stray capacitances comprises surrounding the sides of the gate on either side of its length with air (vacuum) spacers instead of conventionally using spacers made of a solid dielectric material. This is, for example, described in article “Air Spacer MOSFET Technology for 20 nm Node and Beyond” by Jemin Park and Chenming Hu, 9th ICSICT—Oct. 20-23, 2008—IEEE 2008.
Appended FIG. 1 is a copy of FIG. 3(d) of this article. It shows a MOS transistor at an intermediate manufacturing step. This transistor is formed on a substrate covered with a gate stack. On either side of the gate are formed source and drain regions (S/D). The upper surface of the gate supports an oxide (Mask Oxide). The gate and the oxide covering it are surrounded with air spacers. Self-aligned contact (SAC) regions respectively contacting the source and drain regions can be found on either side of these spacers. The entire structure is coated with an insulating layer (ILD2). The air spacers illustrated in FIG. 1 result from the removal by etching of dielectric spacers previously formed on either side of the gate.
This article is an example only of documents of the state of the art relating to air-spacer structures. U.S. Pat. No. 6,001,695 of Texas Instruments and U.S. Pat. No. 7,132,342 of National Semiconductor can also be mentioned.
It would be desirable to further decrease the stray gate capacitances of an air-spacer MOS transistor.